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low skew, 1-to-12, differential-to- 3.3v, 2.5v lvpecl fanout buffer ICS853S12I idt ? / ics ? lvpecl fanout buffer 1 ics853s12aki rev. a may 21, 2008 g eneral d escription the ICS853S12I is a low skew, 1-to-12 differential- to-3.3v, 2.5v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the pclk, npclk pair accepts lvpecl, cml, and sstl differential input levels. the high gain differential amplifier accepts peak-to-peak input voltages as small as 150mv, as long as the common mode voltage is within the specified minimum and maximum range. guaranteed output and part-to-part skew characteristics make the ICS853S12I ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures ? twelve differential 3.3v, 2.5v lvpecl outputs ? pclk, npclk input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, cml, sstl ? maximum output frequency: 1.5ghz ? translates any single-ended input signal to 2.5v or 3.3v lvpecl levels with a resistor bias on npclk input ? additive phase jitter, rms: 0.06ps (typical) ? output skew: 50ps (maximum) ? part-to-part skew: 250ps (maximum) ? propagation delay: 680ps (maximum) ? full 3.3v or 2.5v operating supply modes ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package b lock d iagram p in a ssignment hiperclocks? ic s 24 23 22 21 20 19 18 17 nq7 q7 nq6 q6 nq5 q5 nq4 q4 q11 nq11 v ee pclk npclk v ee q0 nq0 q1 nq1 v cc q2 nq2 q3 nq3 v cc v cc q8 nq8 q9 nq9 v cc q10 nq10 ICS853S12I 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 pclk npclk q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q11 nq11 q10 nq10 q9 nq9 q8 nq8 q7 nq7 q6 nq6 pullup/pulldown pulldown
idt ? / ics ? lvpecl fanout buffer 2 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. c lock i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 11 1 q n , 1 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 , 3v e e r e w o p. s n i p y l p p u s e v i t a g e n 4k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5k l c p nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 8 , 70 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 1 , 91 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 3 , 5 2 , 6 1 , 1 1v c c r e w o p. s n i p y l p p u s e v i t i s o p 3 1 , 2 12 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 13 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 14 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 15 q n , 5 qt u p t u o. . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 26 q n , 6 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 27 q n , 7 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 29 q n , 9 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 28 q n , 8 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 3 , 1 30 1 q n , 0 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l c pk l c p n1 1 q : 0 q1 1 q n : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 2f p r p u l l u p r o t s i s e r p u l l u p t u p n i 0 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 0 5k
idt ? / ics ? lvpecl fanout buffer 3 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v5%, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 7 3 1a m supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja for 32 lead vfqfn 42.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. func- tional operation of product at these conditions or any con- ditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect product reliability. a bsolute m aximum r atings t able 4b. p ower s upply dc c haracteristics , v cc = 2.5v5%, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 0 3 1a m t able 4c. lvpecl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c pv c c v = n i v 5 2 6 . 2 r o v 5 6 4 . 3 =0 5 1a k l c p nv c c v = n i v 5 2 6 . 2 r o v 5 6 4 . 3 =0 1a i l i t n e r r u c w o l t u p n i k l c p v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 1 -a k l c p n v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 00 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 1 +v c c v v h o 3 e t o n ; e g a t l o v h g i h t u p t u ov c c 3 . 1 -v c c 8 . 0 -v v l o 3 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 6 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . 0 5 h t i w d e t a n i m r e t s t u p t u o : 3 e t o n v o t c c . v 2 -
idt ? / ics ? lvpecl fanout buffer 4 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer t able 5. ac c haracteristics , v cc = 3.3v5% or , v cc = 2.5v5%, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 . 1z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p 0 0 30 8 6s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r : e g n a r n o i t a r g e t n i , z h m 2 2 6 z h m 0 2 ? z h k 2 1 6 0 . 0s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 5s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 2s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 80 0 3s p c d oe l c y c y t u d t u p t u o 7 43 5% . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? lvpecl fanout buffer 5 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer a dditive p hase j itter additive phase jitter 622mhz (12khz to 20mhz) = 0.06ps typical the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
idt ? / ics ? lvpecl fanout buffer 6 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer p arameter m easurement i nformation d ifferential i nput l evel o utput l oad 2.5v ac t est c ircuit o utput l oad 3.3v ac t est c ircuit p art - to -p art s kew o utput r ise /f all t ime nqx qx nqy qy part 1 part 2 t sk(pp) v cmr cross points v pp v ee v cc 20% 80% 80% 20% t r t f v sw i n g t pd scope qx nqx lvpecl v ee 2v v cc npclk pclk o utput d uty c ycle /p ulse w idth /p eriod p ropagation d elay -1.3v 0.165v scope qx nqx lvpecl v ee 2v v cc -0.5v 0.125v pclk npclk q0:q11 nq0:nq11 t pw t period t pw t period odc = x 100% q0:q11 nq0:nq11 o utput s kew t sk(o) nqx qx nqy qy q0:q11 nq0:nq11
idt ? / ics ? lvpecl fanout buffer 7 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer a pplication i nformation w iring the d ifferential i nput to a ccept s ingle e nded l evels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. o utputs : lvpecl o utputs : all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. r ecommendations for u nused o utput p ins single ended clock input v cc pclk npclk r1 c1 0.1u r2 1k 1k v_ref
idt ? / ics ? lvpecl fanout buffer 8 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer lvpecl c lock i nput i nterface the pclk /npclk accepts lvpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggest- ed here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termin- ation requirements. f igure 2a. h i p er c lock s pclk/npclk i nput d riven b y a cml d river f igure 2b. h i p er c lock s pclk/npclk i nput d riven b y a b uilt -i n p ullup cml d river f igure 2c. h i p er c lock s pclk/npclk i nput d riven b y a 3.3v lvpecl d river pclk/npclk 2.5v zo = 60 ohm sstl hipercloc ks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 2e. h i p er c lock s pclk/npclk i nput d riven b y a n sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm 3.3v r5 100 - 200 3.3v 3.3v hipercloc ks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 2d. h i p er c lock s pclk/npclk i nput d riven b y a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
idt ? / ics ? lvpecl fanout buffer 9 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer f igure 3. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p at h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base pac kage, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? lvpecl fanout buffer 10 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are rec- ommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination t ermination for 3.3v lvpecl o utputs
idt ? / ics ? lvpecl fanout buffer 11 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer t ermination for 2.5v lvpecl o utputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
idt ? / ics ? lvpecl fanout buffer 12 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS853S12I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS853S12I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 137ma = 474.7mw ? power (outputs) max = 32mw/loaded output pair if all outputs are loaded, the total power is 12 * 32mw = 384mw total power _max (3.465v, with all outputs switching) = 474.7mw + 384mw = 858.7mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 42.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.859w * 42.7c/w = 121.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja vs. air flow (meter per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w t able 6. t hermal r esistance ja for 32 l ead vfqfn, f orced c onvection
idt ? / ics ? lvpecl fanout buffer 13 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.8v (v cc_max - v oh_max ) = 0.8v ? for logic low, v out = v ol_max = v cc_max ? 1.6v (v cc_max - v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.8v)/50 ] * 0.8v = 19.2mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.6v)/50 ] * 1.6v = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32mw f igure 6. lvpecl d river c ircuit and t ermination v out v cc v cc - 2v q1 rl 50
idt ? / ics ? lvpecl fanout buffer 14 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer r eliability i nformation t ransistor c ount the transistor count for ICS853S12I is: 475 t able 7. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. air flow (meter per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
idt ? / ics ? lvpecl fanout buffer 15 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer t able 8. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 0 . 5 2 e 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0 p ackage o utline - k s uffix for 32 l ead vfqfn note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8 below.
idt ? / ics ? lvpecl fanout buffer 16 ics853s12aki rev. a may 21, 2008 ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t f l i k a 2 1 s 3 5 8l i a 2 1 s 3 5 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l i k a 2 1 s 3 5 8l i a 2 1 s 3 5 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ICS853S12I low skew, 1-to-12, differential-to-3.3v, 2.5v lvpecl fanout buffer innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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